Queued consecutive borderline interface (QSPI) and Multichannel buffered consecutive anchorage (MCBSP)
The queued consecutive borderline interface (QSPI) is one blazon of SPI controller, not addition bus type. It uses a abstracts chain with programmable chain pointers acceptance some abstracts transfers after CPU intervention.5 It aswell has a wrap-around approach acceptance connected transfers to and from the chain with no CPU intervention. As a result, the peripherals arise to the CPU as memory-mapped alongside devices. This affection is advantageous in applications such as ascendancy of an A/D converter. Added programmable appearance in QSPI are dent selects and alteration length/delay.
SPI controllers from altered vendors abutment altered affection sets; such DMA queues are not uncommon, although they may be associated with abstracted DMA engines rather than the SPI ambassador itself (MCBSP).6 A lot of SPI adept controllers accommodate abutment for up to four dent selects,7 although some crave dent selects to be managed alone through GPIO lines.
edit Microwire
Microwire is about a antecedent of SPI. It's a austere subset: bisected duplex, and application SPI approach 0. (Microwire-Plus supports added SPI modes.) Microwire chips tend to charge slower alarm ante than newer SPI versions; conceivably 2 MHz vs. 20 MHz. Some Microwire chips aswell abutment a 3-Wire approach (see below), which fits neatly with the brake to bisected duplex.
edit 3-wire consecutive buses
As mentioned above, one alternative of SPI uses individual bidirectional abstracts band (Slave Out/Slave IN, alleged SISO) instead of two unidirectional ones (MOSI and MISO). Clearly, this alternative is belted to a bisected bifold mode. It tends to be acclimated for lower achievement parts, such as baby EEPROMs acclimated alone during arrangement startup and assertive sensors, and Microwire. As of this writing, few SPI adept controllers abutment this mode; although it can generally be calmly bit-banged in software.
When anyone says a allotment supports SPI or Microwire, you can commonly accept that agency the four-wire version.
However, if anyone talks about a allotment acknowledging a 3-wire consecutive bus you should consistently acquisition out what it means: accepted 4-wire SPI, after the dent baddest pin from that count, back a lot of buses use dent selects but alone three affairs backpack "real" signals; (More, sometimes with an distinct SPI bus articulation the device's dent baddest will be hard-wired as "always selected".) "real" 3-wire SPI; or even a RS232 cable with RXD, TXD, and shield/ground, or an application-specific signaling scheme.
edit Multi I/O SPI
As against to 3-wire consecutive buses, multi I/O SPI uses assorted alongside abstracts curve (e.g. IO0 to IO3) to access throughput. Dual I/O SPI application two abstracts curve has commensurable throughput to fast individual I/O (MISO/MOSI). Quad I/O SPI application four abstracts curve has about bifold the throughput.8 Multi I/O SPI accessories tend to be bisected bifold agnate to 3-Wire accessories to abstain abacus too abounding pins. These consecutive anamnesis accessories amalgamate the advantage of added acceleration with bargain pin calculation as compared to alongside memory.
The queued consecutive borderline interface (QSPI) is one blazon of SPI controller, not addition bus type. It uses a abstracts chain with programmable chain pointers acceptance some abstracts transfers after CPU intervention.5 It aswell has a wrap-around approach acceptance connected transfers to and from the chain with no CPU intervention. As a result, the peripherals arise to the CPU as memory-mapped alongside devices. This affection is advantageous in applications such as ascendancy of an A/D converter. Added programmable appearance in QSPI are dent selects and alteration length/delay.
SPI controllers from altered vendors abutment altered affection sets; such DMA queues are not uncommon, although they may be associated with abstracted DMA engines rather than the SPI ambassador itself (MCBSP).6 A lot of SPI adept controllers accommodate abutment for up to four dent selects,7 although some crave dent selects to be managed alone through GPIO lines.
edit Microwire
Microwire is about a antecedent of SPI. It's a austere subset: bisected duplex, and application SPI approach 0. (Microwire-Plus supports added SPI modes.) Microwire chips tend to charge slower alarm ante than newer SPI versions; conceivably 2 MHz vs. 20 MHz. Some Microwire chips aswell abutment a 3-Wire approach (see below), which fits neatly with the brake to bisected duplex.
edit 3-wire consecutive buses
As mentioned above, one alternative of SPI uses individual bidirectional abstracts band (Slave Out/Slave IN, alleged SISO) instead of two unidirectional ones (MOSI and MISO). Clearly, this alternative is belted to a bisected bifold mode. It tends to be acclimated for lower achievement parts, such as baby EEPROMs acclimated alone during arrangement startup and assertive sensors, and Microwire. As of this writing, few SPI adept controllers abutment this mode; although it can generally be calmly bit-banged in software.
When anyone says a allotment supports SPI or Microwire, you can commonly accept that agency the four-wire version.
However, if anyone talks about a allotment acknowledging a 3-wire consecutive bus you should consistently acquisition out what it means: accepted 4-wire SPI, after the dent baddest pin from that count, back a lot of buses use dent selects but alone three affairs backpack "real" signals; (More, sometimes with an distinct SPI bus articulation the device's dent baddest will be hard-wired as "always selected".) "real" 3-wire SPI; or even a RS232 cable with RXD, TXD, and shield/ground, or an application-specific signaling scheme.
edit Multi I/O SPI
As against to 3-wire consecutive buses, multi I/O SPI uses assorted alongside abstracts curve (e.g. IO0 to IO3) to access throughput. Dual I/O SPI application two abstracts curve has commensurable throughput to fast individual I/O (MISO/MOSI). Quad I/O SPI application four abstracts curve has about bifold the throughput.8 Multi I/O SPI accessories tend to be bisected bifold agnate to 3-Wire accessories to abstain abacus too abounding pins. These consecutive anamnesis accessories amalgamate the advantage of added acceleration with bargain pin calculation as compared to alongside memory.
No comments:
Post a Comment